Position

・ Senior Engineer

Experience and knowledge

・Large scale RTL design over 100k gate in Verilog HDL and VHDL, including architecture investigation, logic design, logic verification, timing optimization for the critical path

・Extracting the verification items from the specification

・Creating the testbench and verifying on the bench

Educational background

・ Bachelor’s degree in computer engineering, electronics, electronics and communications engineering, computer science or similar course

Language

・ English

・ Japanese (not required)

Working days and hours

Mon to Fri, 8am to 5pm

Work location

・ Philippines

・ Germany

・ Japan

Please refer to job description.